View CY28342_4343450.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY28342
High-performance SiS645/650 Pentium(R) 4-Clock Synthesizer
Features
* Supports Pentium 4-type CPUs * 3.3V power supply * Eight copies of PCI clocks * One 48 MHz USB clock * Two copies of ZCLK clocks * One 48 MHz/24MHz programmable SIO clock * Two differential CPU clock pairs * SMBus support with read-back capabilities * Spread Spectrum EMI reduction * Dial-a-Frequency(R) features * Dial-a-RatioTM features * Dial-a-dB(R) features * 48-pin SSOP and TSSOP packages * Watchdog Function
Block Diagram
XIN XOUT PLL1 CPU_STP# IREF FS(0:4) MULT0 VTTPWRGD PCI_STP# PLL2 Power on Latch
/2
Pin Configuration[1]
REF(0:2)
CPU(0:1)T CPU(0:1)C SDCLK AGP(0:1) ZCLK(0:1) PCI(0:5) PCI_F(0:1) 48M 48M_24M#
PD# SDATA SCLK
WD Logic I2C Logic
SRESET#
VDDR **FS0/REF0 **FS1/REF1 **FS2/REF2 VSSR XIN XOUT VSSZ ZCLK0 ZCLK1 VDDZ *SRESET#/PCI_STP# VDDP **FS3/PCI_F0 **FS4/PCI_F1 PCI0 PCI1 VSSP VDDP PCI2 PCI3 PCI4 PCI5 VSSP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDSD SDCLK VSSSD CPU_STP#* CPU1T CPU1C VDDC VSSC CPU0T CPU0C IREF VSSA VDDA SCLK SDATA PD#/VTTPWRGD* VSSAGP AGP0 AGP1 VDDAGP VDD48M 48M 24_48M/MULT0* VSS48M
48 Pin SSOP andf TSSOP
Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
CY28342
Page 1 of 21
www.SpectraLinear.com
CY28342
Table 1. Frequency Table FS(4:0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 CPU (MHz) 100.20 133.45 100.20 133.45 100.20 133.33 100.20 133.33 100.20 145.00 111.11 166.60 66.80 66.80 100.20 100.20 100.20 100.20 102.20 133.40 105.00 83.33 108.00 83.33 116.00 83.33 120.00 95.00 112.00 75.00 108.00 95.00 SDRAM (MHz) 100.20 133.45 133.60 100.09 167.00 166.66 150.30 66.67 120.24 145.00 133.33 133.28 66.80 66.80 133.60 133.60 167.00 167.00 136.27 200.10 140.00 138.89 144.00 104.16 145.00 166.67 150.00 142.50 140.00 125.00 180.00 158.33 ZCLK (MHz) 66.80 66.73 66.80 66.73 62.63 66.67 66.80 66.67 66.80 64.44 66.67 66.64 66.80 50.10 100.20 80.16 83.50 100.20 68.13 66.70 70.00 69.44 72.00 69.44 64.44 62.50 66.67 63.33 62.22 62.50 67.50 79.17 AGP (MHz) 66.80 66.73 66.80 66.73 62.63 66.67 66.80 66.67 66.80 64.44 66.67 66.64 66.80 50.10 66.80 66.80 62.63 62.63 68.13 66.70 70.00 69.44 72.00 69.44 64.44 62.50 66.67 63.33 62.22 62.50 67.50 79.17 PCI (MHz) 33.40 33.365 33.40 33.365 31.315 33.335 33.40 33.335 33.40 32.22 33.335 32.22 33.40 25.05 33.40 33.40 31.315 31.315 34.065 33.35 35.00 34.72 36.00 34.72 32.22 31.25 33.335 31.665 31.11 31.25 33.75 39.585 VCO (MHz) 400.8 533.8 400.8 400.4 501.0 666.7 601.2 533.3 601.2 580.0 666.7 666.4 400.8 400.8 400.8 400.8 501.0 501.0 408.8 400.2 420.0 416.6 432.0 416.6 580.0 500.0 600.0 570.0 560.0 375.0 540.0 475.0
Rev 1.0, November 20, 2006
Page 2 of 21
CY28342
Pin Description
Pin 6 7 39,40,43,44 16,17,20,23 14
[2]
Name XIN XOUT CPU (0:1)T, CPU (0:1)C PCI (0:5) FS3/PCI_F0
PWR
I/O I
Description Oscillator buffer input. Connect to a crystal or to an external clock. Oscillator buffer output. Connect to a crystal. Do not connect when an external clock is applied at XIN. Differential host output clock pairs. See Table 1 for frequencies and functionality. PCI clock outputs. See Table 1. Power-on bidirectional Input/Output (I/O). At power-up, FS3 is the input. When VTTPWRGD transitions to a logic HIGH, FS3 state is latched and this pin becomes PCI_F0 clock output. See Table 1. Power-on bidirectional I/O. At power-up, FS4 is the input. When VTTPWRGD transitions to a logic HIGH, FS4 state is latched and this pin becomes PCI_F1 Clock Output. See Table 1. Power-on bidirectional I/O. At power-up, FS0 is the input. When VTTPWRGD transitions to a logic HIGH, FS0 state is latched and this pin becomes REF0, buffered Output copy of the device's XIN clock. Power-on bidirectional I/O. At power-up, FS1 is the input. When VTTPWRGD is transited to logic LOW, FS1 state is latched and this pin becomes REF1, buffered Output copy of the device's XIN clock. Power-on bidirectional I/O. At power-up, FS2 is the input. When VTTPWRGD is transited to logic LOW, FS2 state is latched and this pin becomes REF2, buffered Output copy of the device's XIN clock. Current reference programming input for CPU buffers. A resistor is connected between this pin and VSS. See Figure 8. Power-down input/VTT power good input. At power-up, VTTPWRGD is the input. When this input is transitions initially from LOW to HIGH, the FS (0:4) and MULT0 are latched. After the first LOW-to-HIGH transition, this pin becomes a PD# input with an internal pull-up. When PD# is asserted LOW, the device enters power-down mode. See power management function. Fixed 48-MHz USB clock output. Power-on bidirectional I/O. At power-up, MULT0 is the input. When VTTPWRGD is transitions to logic HIGH MULT0 state is latched and this pin becomes 24_48M, SIO programmable clock output. HyperZip Clock Outputs. See Table 1. Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data, and an open drain output when acknowledging or transmitting data. Serial Clock Input. Conforms to the SMBus specification. PCI Clock Disable Input. If Byte12 Bit7 = 0, this pin becomes an SRESET# open drain output, and the internal pull-up is not active. See system reset description. System Reset Control Output. If Byte12 Bit7 = 1 (Default), this pin becomes PCI Clock Disable Input. When PCI_STP# is asserted LOW, PCI (0:5) clocks are synchronously disabled in a LOW state. This pin does not affect PCI_F (0:1) if they are programmed to be free-running clocks via the device's SMBus interface. CPU Clock Disable Input. When asserted LOW, CPU (0:1)T clocks are synchronously disabled in a HIGH state and CPU (0:1)C clocks are synchronously disabled in a LOW state.
VDDR VDDC VDDP VDDP
O O O I/O PD I/O PD I/O PD I/O PD I/O PD I I PU
15
FS4/PCI_F1
VDDP
2
FS0/REF0
VDDR
3
FS1/REF1
VDDR
4
FS2/REF2
VDDR
38 33
IREF PD#/VTTPR GD
27 26
48M 24_48M/MUL T0 ZCLK (0:1) SDATA
VDD48M VDD48M
O I/O PU O I/O
9,10 34
VDDZ
35 12
SCLK SRESET#
I O
PCI_STP#
I PU
45
CPU_STP#
I PU
Rev 1.0, November 20, 2006
Page 3 of 21
CY28342
Pin Description (continued)[2]
Pin 47 30,31 48 29 11 1 13,19 42 28 36 18,24 41 8 25 5 46 32 37 Name SDCLK AGP (0:1) VDDSD VDDAGP VDDZ VDDR VDDP VDDC VDD48M VDDA VSSP VSSC VSSZ VSS48M VSSR VSSSD VSSAGP VSSA PWR VDDSD VDDAGP I/O O O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR SDRAM Clock Output. AGP Clock Outputs. See Table 1 for frequencies and functionality. 3.3V power supply for SDRAM clock output. 3.3V power supply for AGP clock output. 3.3V power supply for HyperZip clock output. 3.3V power supply for REF clock output. 3.3V power supply for PCI clock output. 3.3V power supply for CPU clock output. 3.3V power supply for 48-MHz/24-MHz clock output. 3.3V analog power supply. GND for PCI clocks outputs. GND for CPU clocks outputs. GND for HyperZip clocks outputs. GND for 48-MHz/24-MHz clocks outputs. GND for REF clocks outputs. GND for SDRAM clocks outputs. GND for AGP clocks outputs. GND for analog. Description
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface (SDI), various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the SDI initializes to their default setting upon power-up, and therefore the use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte Write, byte Read, block Write, and block Read operations from the controller. For a block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte Write and byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block Write and block Read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte Write and byte Read protocol. The slave receiver address is 11010010 (D2h).
Note: 2. PU = Internal pull-up. PD = internal pull-down. T = Tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 -1.8V, and HIGH = > 2.0V.
Rev 1.0, November 20, 2006
Page 4 of 21
CY28342
Table 2. Command Code Definition Bit 7 (6:0) 0 = Block Read or block Write operation 1 = Byte Read or byte Write operation Byte offset for byte Read or byte Write operations. For block Read or block Write operations, these bits should be "0000000" Description
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command code - 8-bit "00000000" stands for block operation Acknowledge from slave Byte count -8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte N/slave acknowledge... Data byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bit "1xxxxxxx" stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Byte count - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit "1xxxxxxx" stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command code - 8-bit "00000000" stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/acknowledge Data byte N from slave - 8 bits Not acknowledge Stop Block Read Protocol Description
Rev 1.0, November 20, 2006
Page 5 of 21
CY28342
Table 4. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit Description Bit 30:37 38 39 Not acknowledge Stop Byte Read Protocol Description Data byte from slave - 8 bits
Since SDR and DDR Zero Delay Buffers will share this same address, the device starts from Byte 4. Byte 4: CPU Clock Register (All bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup H/W Setting H/W Setting H/W Setting H/W Setting 0 H/W Setting 1 0 15 FS4 SSCG Pin# 14 4 3 2 Name FS3 FS2 FS1 FS0 Description For selecting frequencies in Table 1. For selecting frequencies in Table 1. For selecting frequencies in Table 1. For selecting frequencies in Table 1. 0 = HW, 1 = SW frequency selection. For selecting frequencies in Table 1. Spread Spectrum Enable. 0 = spread off, 1 = spread on. This is a Read and Write control bit. Master output control 0 = running, 1 = three-state all outputs.
Byte 5: CPU Clock Register (all bits are Read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 X X X X X X 26 15 14 4 3 2 MULT0 FS4 FS3 FS2 FS1 FS0 Pin# Name Reserved. Reserved. MULT0 (pin 26) value. This bit is Read-only. FS4 Read-back. This bit is Read-only. FS3 Read-back. This bit is Read-only. FS2 Read-back. This bit is Read-only. FS1 Read-back. This bit is Read-only. FS0 Read-back. This bit is Read-only. Description
Byte 6: CPU Clock Register (All bits are Read and Write functional) Bit 7 6 5 4 3 @Pup 0 0 0 0 1 14 15 40,39 PCI_F0 PCI_F1 Pin# Name Reserved. PCI_STP# control of PCI_F0. 0 = free running, 1 = stopped when PCI_STP# is LOW. PCI_STP# control of PCI_F1. 0 = free running, 1 = stopped when PCI_STP# is LOW. Description Function Test Bit. Always program to 0.
Controls CPU0T and CPU0C functionality when CPU_STP# is asserted LOW. CPU0T/C 0 = free running, 1 = stopped with CPU_STP# asserted LOW. This is a Read and Write control bit. Controls CPU1T and CPU1C functionality when CPU_STP# is asserted LOW CPU1T/C 0= Free Running, 1 Stopped with CPU_STP# asserted to LOW. This and Read and Write control bit. CPU0T/C CPU1T/C CPU0T, CPU0C output control, 1= enabled, 0 = disabled. This is a Read and Write control bit. CPU1T, CPU1C output control, 1= enabled, 0 = disabled. This is a Read and Write control bit.
2 1 0
0 1 1
44,43 40,39 44,43
Rev 1.0, November 20, 2006
Page 6 of 21
CY28342
Byte 7: PCI Clock Register (All bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 15 14 23 22 21 20 17 16 Name PCI_F0 PCI_F1 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Description PCI_F0 output control 1 = enabled, 0 = forced LOW. PCI_F1 output control 1 = enabled, 0 = forced LOW. PCI5 output control 1 = enabled, 0 = forced LOW. PCI4 output control 1 = enabled, 0 = forced LOW. PCI3 output control 1 = enabled, 0 = forced LOW. PCI2 output control 1 = enabled, 0 = forced LOW. PCI1 output control 1 = enabled, 0 = forced LOW. PCI0 output control 1 = enabled, 0 = forced LOW.
Byte 8: Silicon Signature Register (all bits are Read-only) Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 Revision ID Vendor ID 1000 = Cypress Description
Byte 9: Peripheral Control Register (All bits are Read and Write) Bit 7 6 5 4 3 2 1 0 @Pup 1 0 1 1 0 0 0 0 27 26 26 48M 48M_24M 48M_24M Pin# 33 Name PD# Description PD# Enable. 0 = enable, 1 = disable. 0 = when PD# asserted LOW, CPU(0:1)T stop in a high state, CPU(0:1)C stop in a LOW state. 1 = when PD# asserted LOW, CPU(0:1)T and CPU(0:1)C stop in H-Z. 48M output control 1 = enabled, 0 = forced LOW. 48M_24M output control 1 = enabled, 0 = forced LOW. 48M_24M, 0 = pin 26 output is 24MHz, 1= pin 28 output is 48 MHz. SS2 Spread Spectrum control bit (0= down spread, 1= center spread). SS1 Spread Spectrum control bit. See Table 10. SS0 Spread Spectrum control bit. See Table 10.
Byte 10: Peripheral Control Register (All bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 47 4 3 2 10 9 30 31 Name SDCLK REF2 REF1 REF0 ZCLK1 ZCLK0 AGP1 AGP0 Description SDCLK output enable 1 = enabled, 0 = disabled. REF2 output control 1 = enabled, 0 = forced LOW. REF1 output control 1 = enabled, 0 = forced LOW. REF0 output control 1 = enabled, 0 = forced LOW. ZCLK1 output enable 1 = enabled, 0 = disabled. ZCLK0 output enabled 1 = enabled, 0 = disabled. AGP1 output enabled 1 = enabled, 0 = disabled. AGP0 output enabled 1 = enabled, 0 = disabled.
Rev 1.0, November 20, 2006
Page 7 of 21
CY28342
Byte 11: Dial-a-SkewTM and Dial-a-RatioTM Control Register (All bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Description DARSD2 Programming these bits allows modifying the frequency ratio of the SDCLK clock relative to the VCO. DARSD1 See Table 5. DARSD0 DARAG2 Programming these bits allows modifying the frequency ratio of the AGP(1:0), PCI(5:0) and PCIF(0:1) DARAG1 clocks relative to the VCO. See Table 6. DARAG0 DASSD1 Programming these bits allows shifting skew between CPU and SDCLK signals. See Table 7. DASSD0
Table 5. Dial-a-Ratio SDCLK DARSD (2:0) 000 001 010 011 100 101 110 111 Table 6. Dial-a-Ratio AGP(0:1)[3] DARAG (2:0) 000 001 010 011 100 101 110 111 Table 7. Dial-a-Skew SDCLK CPU DASSD (1:0) 00 01 10 11 SDCLK-CPU Skew 0 ps (default)[4] +150 ps (CPU lag)* +300 ps (CPU lag)* +450 ps (CPU lag)* VC0/AGP Ratio Frequency selection default 6 7 8 9 10 10 10 VC0/SDCLK ratio Frequency selection default 2 3 4 5 6 8 9
Notes: 3. The ratio of AGP to PCI is retained at 2:1. 4. See Figure 8 for CPU measurement point. See Figure 9 for SDCLK measurement point.
Rev 1.0, November 20, 2006
Page 8 of 21
CY28342
Byte 12: Watchdog Time Stamp Register (All bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 WD3 WD2 WD1 WD0 Name Description SRESET#/PCI_STP#. 1 = pin 12 is the input pin as PCI_STP# signal. 0 = pin 12 is the output pin as SRESET# signal. Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time-out only. 0 = selects frequency of existing H/W setting. 1 = selects frequency of the second to last S/W setting (the software setting prior to the one that caused a system reboot). WDTEST. For WD-Test, ALWAYS program to "0." WD Alarm. This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). These bits select the Watchdog Time Stamp Value. See Table 8.
Table 8. Watchdog Time Stamp Table WD(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FUNCTION Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds
Byte 13: Dial-a-Frequency Control Register N (All bits are Read and Write functional)[5] Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved. N6, MSB N5 N4 N3 N2 N3 N0, LSB Description
Note: 5. Byte 13 and Byte 14 should be Write together in every case.
Rev 1.0, November 20, 2006
Page 9 of 21
CY28342
Byte 14: Dial-a-Frequency Control Register (All bits are Read and Write functional)[5] Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved. R5 MSB R4 R3 R2 R1 R0, LSB R and N Register Load Gate. 0 = gate closed (data is latched), 1= gate open (data is loading from SMBus registers into R and N)#. Description
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via byte 13 and byte 14. P is a large-value, phase-locked loop (PLL) constant that depends on the frequency selection achieved through the hardware selectors FS(4:0). P value may be determined from the following table. Table 9. FS(4:0) 00000, 00001, 00010, 00111, 01001, 01011, 01110, 01111, 10010, 10100, 10110 00100, 00101, 10000, 10001, 10101, 10111, 11000, 11010, 11100, 11101, 11110, 11111 00110, 01000, 01010, 01100, 01101, 11001, 11011 00011, 10011 P 95996900 76797520 63997933 127995867
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to minimize electromagnetic interference (EMI) radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center of the frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth, thereby causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. See the SMBus register section of this data sheet for the exact bit and byte functionally. The following table is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Table 10.Spread Spectrum SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Center Center Center Center Spread% 0, -0.50 +0.12, -0.62 +0.25, -0.75 +0.50, -1.00 +0.25, -0.25 +0.37, -0.37 +0.50, -0.50 +0.75, -0.75
Rev 1.0, November 20, 2006
Page 10 of 21
CY28342
System Self-recovery Clock Management
This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. When the system sends an SMBus command requesting a frequency change through byte 4 or through bytes 13 and 14, it must have previously sent a command selecting which time-out stamp the Watchdog must perform to byte 12, or the system self-recovery feature will not be applicable. Consequently this device will change frequency, and then the Watchdog timer starts timing. Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in byte 12, bits(3:0) (reprogram to 0000) before Watchdog times out, this device will keep operating in its normal condition with the new selected frequency. If the Watchdog times out the first time before the new SMBus reprograms byte 12, bits(3:0) to (0000), then this device will send a low system reset pulse, on SRESET# (see byte 12, bit 7), and changes the Watchdog alarm (byte 12, bit 4) status to "1" then restarts the Watchdog timer. If the Watchdog times out a second time, this device will send another low pulse on SRESET#, will relatch original hardware strapping frequency (or second-to-last software-selected frequency, see byte 12, bit6) selection, set Watchdog alarm bit (byte 12, bit4) to "1," then start the Watchdog timer again. The above-described sequence will keep repeating until the BIOS clears the SMBus byte 12 bits(3:0). Once the BIOS sets byte 12 bits(3:0) = 0000, the Watchdog timer is turned off and the Watchdog alarm bit (byte 12, bit 4) is reset to "0."
S y s t e m r u n n in g w it h o r ig in a lly s e le c t e d f r e q u e n c y v ia h a r d w a r e s t r a p p in g .
No F r e q u e n c y w ill c h a n g e b u t S y s t e m S e lf R e c o v e r y n o t a p p lic a b le ( n o t im e s t a m p s e le c t e d a n d b y t e 1 2 , b it ( 3 : 0 ) is s t ill = "0 0 0 0 " R e c e iv e F r e q u e n c y C h a n g e R e q u e s t v ia S M B u s B y t e 4 o r V ia D ia la -fre q u e n c y ? Y es
No Is S M B u s B y te 9 , tim e o u t s t a m p e n a b le d - ( b y t e 1 2 , b it (3 :0 ) 0 0 0 0 )?
C h a n g e to a n e w fre q u e n c y
1 ) S e n d a n o th e r 3 m S lo w p u ls e o n S R E S E T 2 ) R e la t c h o r ig in a l h a r d w a r e s t r a p p in g s e le c t io n f o r r e t u r n t o o r ig in a l f r e q u e n c y s e t t in g s . 3 ) S e t W D A la r m b it ( b y t e 1 2 , B it 4 ) t o " 1 " 4 ) S ta r t W D tim e r Y es 1) Send SRESET p u ls e 2 ) S e t W D b it ( b y t e 1 2 , b it 4 ) t o '1 ' 3 ) S t a r t W D t im e r Yes
Yes S t a r t in t e r n a l w a t c h d o g t im e r .
W a t c h D o g t im e o u t ?
W a t c h D o g t im e o u t ?
No
No S M B u s b y te 1 2 tim e o u t s t a m p d is a b le d ? S M B u s b y te 9 tim e o u t s t a m p d is a b le d , B y t e 1 2 , b it ( 3 : 0 ) = ( 0 0 0 0 ) ? Yes Yes T u r n o ff w a tc h d o g tim e r . K e e p n e w f r e q u e n c y s e t t in g . S e t W D a la r m b it ( b y t e 1 2 , b it 4 ) t o ''0 ' No
No
Table 11.CPU Clock Current Select Function
Mult0 0 1 Board Target Trace/Term Z 50 Ohms (not used) 50 Ohms Reference R, Iref - VDD (3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current IOH = 4*Iref IOH = 6*Iref Voh @ Z 1.0V @ 50 0.7V @ 50
Table 12.Group Timing Relationship and Tolerances
Offset CPU to SDCLK CPU to AGP CPU to ZCLK CPU to PCI Typical 0 ns Typical 2 ns Typical 2 ns Typical 2 ns Tolerance(or Range) 2 ns 1-4ns 1-4ns 1-4ns Conditions CPU leads CPU leads CPU leads CPU leads Notes Note 6 Note 6 Note 6 Note 6
Rev 1.0, November 20, 2006
Page 11 of 21
CY28342
Table 12.Group Timing Relationship and Tolerances
Note: 6. See Figure 8 for CPU clock-measurement point. See Figure 9 for SDCLK, AGP, ZCLK and PCI output-measurement points.
Rev 1.0, November 20, 2006
Page 12 of 21
CY28342
CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting of the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# Assertion When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPU clock edges. The final state of the stopped CPU signals is CPU = HIGH and CPU0# = LOW. There is no change to the output drive current values during the stopped state. The CPU is driven HIGH with a current value equal to (Mult0 "select") x (Iref), and the CPU# signal will not be driven. Due to external pull-down circuitry, CPU# will be LOW during this stopped state. CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
CPU_STP# CPUT CPUC
Figure 1. Assertion CPU_STP# Waveform
CPU_STP# CPUT CPUC CPUT CPUC
Figure 2. Deassertion CPU_STP# Waveform
Rev 1.0, November 20, 2006
Page 13 of 21
CY28342
PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup). (See Figure 3.) The PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running. PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level.
t setup
PCI_STP# PCI_F(0:2) 33M PCI(0:6) 33M
Figure 3. Assertion PCI_STP# Waveform
t setup
PCI_STP# PCI_F(0:2) PCI(0:6)
Figure 4. Deassertion PCI_STP# Waveform[7]
Note: 7. The PCI STOP function is controlled by 2 inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These 2 inputs are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device's stoppable PCI clocks are not running.
Rev 1.0, November 20, 2006
Page 14 of 21
CY28342
PD# (Power-Down) Clarification The PD# (power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low "stopped" state. PD# - Assertion (transition from logic "l" to logic "0") When PD# is sampled LOW by two consecutive rising edges of CPUC clock then all clock outputs (except CPUT) clocks must be held LOW on their next HIGH-to-LOW transition. CPUT clocks must be hold with CPUT clock pin driven HIGH with a value of 2x Iref and CPUC undriven. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# Deassertion (transition from logic "0" to logic "1") The power-up latency between PD# rising to a valid logic "1" level and the starting of all clocks is less than 3.0 ms.
PD #
C PU (0:1)T
C PU (0:1)C C PU Internal
C PU # Internal
Figure 5. Power-down Assertion/Deassertion Timing Waveforms - Nonbuffered Mode
VID (0:3), SEL (0,1) VTTPWRGD PWRGD
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
Wait for VTT_GD#
Sample Sels State 2 State 3 (Note A)
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 6. VTTPWRGD Timing Diagram[8]
Note: 8. Device is not affected; VTTPWRGD is ignored.
Rev 1.0, November 20, 2006
Page 15 of 21
CY28342
TP W = H RG ig h D
S1
S2
D e la y 0 .25 m S
S a m p le In p u ts F S (3 :0 )
W a it fo r 1 .1 4 6 m s
VT
E n a b le O u tpu te s Outputs
V D D A = 2 .0 V
S0
S3
P o w er O ff
V D D 3.3 = O ff
N o rm a l O p e ra tio n
Figure 7. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 20, 2006
Page 16 of 21
CY28342
Maximum Ratings
Input Voltage Relative to VSS................................VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature:..................................-65 C to +150 C Operating Temperature: ....................................0 C to +70 C Maximum Power Supply: ............................................... 3.5V
DC Characteristics
Current Accuracy[9] Conditions Iout VDD = nominal (3.30V) Configuration M0= 0 or 1 and Rr shown in table Load Nominal test load for given configuration Nominal test load for given configuration Min. -7% Inom Max. +7% Inom
Iout
VDD = 3.30 5%
All combinations of M0 or 1 and Rr shown in table
-12% Inom
+12% Inom
DC Component Parameters (VDD =3.3V5%, TA = 0C to 70C) Parameter Idd3.3V Ipd3.3V Cin Cout Lpin Cxtal Description Dynamic Supply Current Power-down Supply Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance 30 36 Min. Typ. Max. 280 Note 11 5 6 7 42 Units mA mA pF pF nH pF Measured from the XIN or XOUT Pin to Ground Conditions All frequencies at maximum values[10] PD# Asserted
AC Parameters
100 MHz Parameter Crystal TDC TPeriod VHIGH VLOW Tr/Tf TCCJ XIN Duty Cycle XIN period XIN HIGH Voltage XIN LOW Voltage XIN Rise and Fall Times XIN Cycle to Cycle Jitter Description Min. 47.5 69.841 0.7VDD 0 Max. 52.5 71.0 VDD 0.3VDD 10.0 500 150 150 45 9.8 55 10.2 45 7.35 133 MHz Min. 47.5 69.841 0.7VDD 0 Max. 52.5 71.0 VDD 0.3VDD 10.0 500 150 150 55 7.65 Unit % ns V V ns ps ps ps % ns 13,14,16 16, 17, 18 16, 17, 18 16, 17, 18 16, 17, 18 Notes 12,13 12,13,14,15
CPU at 0.7V Timing TSKEW Any CPU to CPU Clock Skew TCCJ TDC TPeriod CPU Cycle to Cycle Jitter CPU and CPUC Duty Cycle CPU and CPUC Period
Notes: 9. Inom refers to the expected current based on the configuration of the device. 10. All outputs loaded as per maximum capacitive load table. 11. Absolute value = (programmed CPU Iref 97) +10 mA. 12. This parameter is measured as an average over 1 s duration with a crystal center frequency of 14.318 MHz. 13. When XIN is driven from an external clock source. 14. All outputs loaded per Table 13 below. 15. Probes are placed on pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section). 16. This measurement is applicable with Spread ON or Spread OFF. 17. Measured at crossing point (Vx), or where subtraction of CLK-CLK# crosses 0V. 18. For CPU load. See Figure 8.
Rev 1.0, November 20, 2006
Page 17 of 21
CY28342
AC Parameters (continued)
100 MHz Parameter Tr/Tf DeltaTr DeltaTf Vcross AGP TDC TPeriod THIGH TLOW Tr/Tf Tskew Unbuffered TCCJ ZCLK TDC Tr/Tf TSKEW TCCJ PCI TDC TPeriod THIGH TLOW Tr/Tf TSKEW TCCJ SDCLK TDC TPeriod THIGH TLOW Tr/Tf TCCJ 48M TDC TPeriod Tr/Tf TCCJ Description CPU and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Crossing Point Voltage at 0.7V Swing AGP Duty Cycle AGP Period AGP HIGH Time AGP LOW Time AGP Rise and Fall Times Any AGP to Any AGP Clock Skew AGP Cycle-to-Cycle Jitter ZCLK(0:1) Duty Cycle ZCLK(0:1) Rise and Fall Times Any ZCLK(0:1) to Any ZCLK(0:1) Skew ZCLK(0:1) Cycle-to-Cycle Jitter PCI_F(0:1) PCI (0:5) Duty Cycle PCI_F(0:1) PCI (0:5) Period PCI_F(0:1) PCI (0:5) HIGH Time PCI_F(0:1) PCI (0:5) LOW Time PCI_F(0:1) PCI (0:5) Rise and Fall times Any PCI Clock to Any PCI Clock Skew PCI_F(0:1) PCI (0:5) Cycle-to-Cycle Jitter SDCLK Duty Cycle SDCLK Period SDCLK HIGH Time SDCLK LOW Time SDCLK Rise and Fall Times SDCLK Cycle-to-Cycle Jitter 48M Duty Cycle 48M Period 48M Rise and Fall Times 48M Cycle-to-Cycle Jitter 45 9.8 3.0 2.8 0.4 - 45 1.0 1.6 250 55 2.0 350 45 30.0 12.0 12.0 0.5 2.0 500 250 55 10.2 45 7.35 1.87 1.67 0.4 - 45 1.0 1.6 250 55 2.0 350 45 0.5 280 45 15.0 5.25 5.05 0.5 1.6 175 250 55 1.6 175 250 55 45 30.0 12.0 12.0 0.5 2.0 500 250 55 7.65 45 0.5 Min. 175 Max. 700 20% 125 125 430 55 15.3 280 45 15.0 5.25 5.05 0.5 1.6 175 250 55 1.6 175 250 55 133 MHz Min. 175 Max. 700 20% 125 125 430 55 15.3 ps ps mV % ns ns ns ns ps ps % ns ps ps % nS nS nS nS ps ps % ns ns ns ns ps % ns ns ps Unit ps Notes 16,19 18,19,20 18,19 18,19 17,18,19 14, 15 14, 15 21 22 14, 23 14, 15 14, 15 14, 15 14, 23 14, 15 14,15 14, 15 12,14,15 21 22 14, 23 14, 15 14, 15 14, 15 14, 15 21 22 14, 23 14, 23 14, 15 14, 15 14, 23 14, 15
20.829 20.834 20.829 20.834
Notes: 19. Measured from VOL = 0.175 to VOH = 0.525V. 20. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall). 21. THIGH is measured at 2.4V for all non-host outputs. 22. TLOW is measured at 0.4V for all non-host outputs. 23. Probes are placed on pins and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section).
Rev 1.0, November 20, 2006
Page 18 of 21
CY28342
AC Parameters (continued)
100 MHz Parameter 24M TDC TPeriod Tr/Tf TCCJ REF TDC TPeriod Tr/Tf TCCJ Description 24-MHz Duty Cycle 24-MHz Period 24-MHz Rise and Fall Times 24-MHz Cycle-to-Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle-to-Cycle Jitter 1.0 1.0 10.0 0 45 69.8413 1.0 Min. 45 41.66 1.0 Max. 55 41.67 4.0 500 55 71.0 4.0 1000 10.0 10.0 1.5 10.0 0 1.0 1.0 45 69.8413 1.0 133 MHz Min. 45 41.66 1.0 Max. 55 41.67 4.0 500 55 71.0 4.0 1000 10.0 10.0 1.5 Unit % ns ns ps % ns ns ps ns ns ms ns ns 24 Notes 14, 15 14, 15 14, 23 14, 15 14, 15 14, 15 14, 23 14, 15
ENABLE/DISABLE and SET UP tpZL, tpZH Output Enable Delay (All Outputs) tpLZ, tpZH tstable tss tsh Output Disable Delay (All Outputs) All Clock Stabilization from Power-up Stopclock Set-up Time Stopclock Hold Time
Table 13.Maximum Lumped Capacitive Output Loads Clock PCI(0:5), PCI_F(0:1) AGP (0:1), SDCLK ZCLK (0:1) 48M_24, 48M Clock REF (0:2) CPU(0:1)T CPU(0:1) C Max. Load 30 30 30 20 30 2 Units pF pF pF pF pF pF
Notes: 24. CPU_STP# and PCI_STP# set-up time with respect to any PCI_F clock to guarantee that the affected clock will stop or start at the next PCI_F clock's rising edge. 25. When crystal meets minimum 40 ohm device series resistance specification. 26. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70, but the REF clock duty cycle will not be within data sheet specifications.
Rev 1.0, November 20, 2006
Page 19 of 21
CY28342
Test and Measurement Set-up
For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
33
T PCB
49.9 2 pF
CPUT
Measurem ent Point
MULTSEL
33
T PCB
49.9 2 pF
Measurem ent Point
CPUC IREF
475
Figure 8. 0.7V Configuration
O u tp u t u n d e r T e s t P ro b e
Load Cap
3 .3 V s ig n a l s
tD C
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
Tr
Tf
Figure 9. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number CY28342OC CY28342OCT CY28342ZC CY28342ZCT Package Type 48-pin Shrunk Small Outline Package (SSOP) 48-pin Shrunk Small Outline Package (SSOP) - Tape and Reel 48-pin Thin Shrunk Small Outline Package (TSSOP) Product Flow Commercial 0 to 70 C Commercial 0 to 70 C Commercial 0 to 70 C
48-pin Thin Shrunk Small Outline Package (TSSOP) - Tape and Reel Commercial 0 to 70 C
Rev 1.0, November 20, 2006
Page 20 of 21
CY28342
Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
48-lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z48
51 85059 *B
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 21 of 21

▲Up To Search▲

Price & Availability of CY28342

	To Download CY28342 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .